The present invention relates to a memory apparatus including a plurality of semiconductor memories, and more particularly to a method and an apparatus for reading plural data respectively stored at the same memory addresses of a plurality of semiconductor memories of the memory apparatus.
In recent year, a flash memory (a flash EEPROM) has attracted attention as a semiconductor memory which is available in place of a magnetic memory, such as a hard disk or a floppy disk. The flash memory is a nonvolatile semiconductor memory which exhibits small electric power consumption and which can be rewritten. Since the flash memory has a light weight and having satisfactory vibration resistance, it has been widely used in a portable apparatus.
In general, a computer system having the flash memory as an external memory device thereof has a controller provided for only the flash memory. A host computer (for example, a personal computer) is required to command the controller to write or read data. The controller receives a command issued from the host computer to directly control the flash memory to write or read data. Moreover, the controller performs memory control, such as batch erase, which is inherent to the flash memory.
Hitherto, a plurality of chips each containing a controller and a plurality of NAND flash memories have been mounted on one card. When the memory card has been loaded into a card slot of the host computer, the controller is connected to the host computer through an interface, such as a PCMCIA-ATA interface of an IDE interface having a predetermined specification.
The controller is, on the card, connected to each flash memory through an internal bus of, for example, 8-bit width, a single common control line for all of the flash memories and control lines respectively assigned to the flash memories.
In the above-mentioned structure, the controller maintains a chip enable control signal at an active level (L level) during the overall reading operation period to maintain the flash memories at a chip enable (active) state.
In this case, the controller initially makes active (H level) the command latch enable control signal to transmit a read command having a predetermined code onto the bus. Simultaneously, the controller makes active (L level) the write enable control signal. As a result, the flash memories fetch the read command in response to the command writing operation performed by the controller.
Then, the controller makes active (H level) the address latch enable control signal to transmit a read address having a predetermined number of bits while dividing the operation into three portions. Whenever the controller transmits the read address, the controller makes active (L level) the write enable control signal. In response to the address write operation performed by the controller, the flash memories fetch the address to start performing the memory reading operation.
That is, the conventional reading method is arranged such that the flash memory decodes the supplied read command and the read address, reads data from a memory address or a region accessed by the read address, and sets read data to a predetermined output port or a buffer. Since the operation for reading the memory takes a predetermined time, the flash memory maintains a busy signal at an active level (L level) during the foregoing processing period to bring the controller to a standby state.
After the operation for reading the flash memory has been completed and thus the busy state has been suspended, the controller starts performing an operation for fetching read data from the output port of the flash memory.
In general, data is, in the form of a group, written/read to and from the flash memory. The read address, which is supplied from the controller to the flash memory to read data, is a memory address from which data is read or an address (head address) instructing a position in a region from which data is read. However, the controller repeatedly makes active (L level) the read enable control signal to fetch data from the output port of the flash memory by one byte at a time through a bus so as to read data in one group from a required memory region in the flash memory accessed by the read address.
A flash memory of the foregoing type has a memory array in the chip thereof which is divided into a plurality of sections, for example, 512 blocks. Each block is divided into a plurality of pages or sectors, for example, 16 pages or 16 sectors. In general, programming (writing) and reading are performed in page units, while deleting is performed in block units.
Each page includes a data region having a predetermined capacity, for example, 512 bytes and a redundant region having a predetermined capacity, for example, 16 bytes. The data region is essential data memory region. The redundant region is sectioned into several fields including a conversion address region. The conversion address region stores a logical address used in writing data whenever data is written on the sector from the host computer.
When viewed from the host computer, the host computer considers the memory region of the flash disk as a predetermined memory space or an I/O space and makes an access to the memory with the logical address. However, the controller administrates the memory regions in the card in block units in a scattering manner and the memory access is made with a physical address. Therefore, an address conversion table for making the logical addresses and the physical addresses to correspond to one another is formed in a table memory (SRAM) included in the controller. In order register empty blocks having no data, also an empty block table is formed in the table memory.
Immediately after power has been turned on or immediately after resetting has been released, the controller initializes the address conversion table and the empty block table. In order to initialize the tables above, the controller performs a process for collecting logical addresses, which have been assigned to all pages in the card. The redundant region of each page stores the logical address (the conversion table address) which has been used in the previous writing operation. The most significant address portion of the logical address, that is, the logical block address is common to all pages in one block. Therefore, data stored in the redundant region of a representative page (which is a head page in general) of each block is required to be read. By extracting the included logical block address, the logical address for each of pages PG0 to PG15 in the block BLj can be detected.
In general, data in the redundant region of the head page of a first block of each of all of the flash memories is sequentially read. Then, data in the redundant region of the head page of a second block of each of all of the flash memories is sequentially read. Then, data in the redundant region of the head page of a third block is sequentially read. Then, a similar reading operation is repeated for the following blocks.
In a flash disk system of the foregoing type, when an operation for reading data from the redundant region of the head page of a N th block of one flash memory is performed at the above-mentioned timing, the controller fetches data of 16 bytes from the output port of the flash memory in the fourth phase while performing all 16 cycles. To sequentially read data from the redundant region of the head page of each of the N th blocks of all of the flash memories, the above-mentioned read cycles have been repeated by a number which is the same as the total number of the flash memories.
In a flash memory of the above-mentioned type, one reading operation includes four phases, i.e., writing (supplying) of a read command to one memory (a first phase); writing (supplying) of a read address on one memory (a second phase); reading of data from one memory (a third phase): and transference of data from the memory to the controller (a fourth phase). Among the four phases above, the third phase takes a long time which mainly shares one reading cycle.
The conventional flash disk system has the structure such that the controller makes an access to the same memory addresses of all of the flash memories in the card such that the controller repeats the reading cycle by the number which is the same as the total number of the memory chips. As a result, a considerably long time is required to complete the reading operation. As a result, the initialization takes an excessively long time, thus raising a problem in that the performance of the memory system deteriorates.